1. Field of the Invention
The present invention relates to a photoflash circuit and particularly to a method and device for charging a photoflash capacitor utilizing an adjustable charge current limit.
2. Description of the Related Art
Cameras that utilize photoflashes typically include a charging circuit that charges a photoflash capacitor included in the camera. The photoflash capacitor stores energy in the form of electrical charge. This energy is later utilized by the photoflash to produce a “flash” when a picture is taken.
Generally, in a camera with a charging circuit, a battery supplies a current at a certain voltage to a step-up transformer, that is part of the charging circuit. The transformer transforms a voltage of approximately 3 volts (the battery's voltage) to a voltage of 300 volts at which the photoflash capacitor is charged. The photoflash capacitor then provides the energy stored thereon to a trigger circuit that, among other things, contributes to stepping up the voltage on the photoflash (flash tube) to about 4000 volts. This voltage causes ionization of the gas inside the flash tube. When the photoflash is triggered, the discharge of the photoflash capacitor through the ionized flash tube generates a very high current therethrough, which thereby causes light in the flash tube.
FIG. 1 shows a circuit diagram of a photoflash capacitor charging circuit disclosed in U.S. Pat. No. 6,518,733. A power delivery circuitry 120 operates to transfer power from an input source 170 to the photoflash capacitor 144 (which is preferably coupled to the load). The power delivery circuitry 120 includes an adaptive ON-time circuitry 130, adaptive OFF-time circuitry 135, transformer 122, switch transistor 124, latch 126, and output diode 142. The power delivery circuitry 120 is coupled to the photoflash capacitor 144 via the output diode 142. The anode of the output diode 142 is coupled to the output side of the secondary winding of the transformer 122 and the cathode of the output diode 142 is coupled to the photoflash capacitor 144. The input source 170 is coupled to the input of the primary side of the transformer 122. The output of the primary side of the transformer 122 is coupled to the collector of the switch transistor 124. The emitter of the switch transistor 124 is coupled to the adaptive ON-time circuitry 130.
The polarity orientation of the primary and secondary windings are preferably arranged so that the respective windings have opposite polarity. As illustrated in FIG. 1, polarity indicators 112 and 114 show that the polarity of the primary and secondary windings are opposite. This opposite polarity is useful for implementing a flyback circuit topology.
The adaptive ON-time circuitry 130 includes a first switch resistor 131, which is coupled to the emitter of the switch transistor 124 to form an ON-time node 134. The ON-time circuitry 130 also includes an ON-time comparator 132. The ON-time comparator 132 is coupled to receive voltage signals from the ON-time node 134 and ON-time reference voltage VREF1 133.
The adaptive OFF-time circuitry 135 includes a second switch resistor 136, which is coupled to the secondary winding of the transformer 122 and to non-inverting terminal of the OFF-time comparator 137. The OFF-time comparator 137 also receives an OFF-time reference voltage −VREF2 138. The OFF-time reference voltage −VREF2 138 is negative because it is compared to the negative voltage across the second switch resistor 136.
The adaptive ON-time circuitry 130 and adaptive OFF-time circuitry 135 each provides output signals that are received by a latch 126. The Latch 126 is, for example, a set/reset latch. In particular, the reset portion of the latch 126 is coupled to receive the output of the ON-time circuitry 130 and the set portion of the latch 126 is coupled to receive the output of the OFF-time circuitry 135. If the latch 126 receives signals simultaneously for both set and reset, the reset input preferably takes priority. The Latch 126 provides a latch output to the base of the switch transistor 124 based on the output signals provided by the ON-time circuitry 130 and OFF-time circuitry 135. The latch output is toggled to activate or de-activate the switch transistor 124 to generate the switching action necessary for DC-to-DC conversion.
Conventionally, in the previously described circuitry, circuits and elements other than the transformer and photoflash capacitor reside in a single IC. The reference voltage VREF2 138 or VREF1 133 is determined once the IC is fabricated, which allows no adaptation of the charge current limit. This is disadvantageous to photoflash or camera system design.